The present invention relates generally to methods of making semiconductor devices. More particularly, the invention relates to a method of removing nano-crystals during the manufacture of a semiconductor device.
Flash memory devices in which electrons are stored in nano-crystals rather than floating gates have been developed. For example, such devices are described in US Application Publication No. 2006/0081911, which is incorporated herein by reference. FIG. 1 shows a floating gate n-channel MOS electron memory device. The memory device 100 includes a substrate 105. The substrate is selected based on the type of device.
There is a first gate insulating layer 110 on the substrate 105. The first gate insulating layer 110 can be made of any suitable insulating material, including, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, a high constant dielectric insulator such as HfSiO, or a stack of layers including at least one barrier layer and at least one high dielectric constant layer. If a high constant dielectric layer is used, a barrier layer (not shown) can be formed between the high constant dielectric layer and the substrate.
Noble metal nano-crystals 115 are formed on the first gate insulating layer 110. The noble metal nano-crystals can be formed using any suitable process, including, but not limited to, chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The noble metal nano-crystals are made of various noble metals including, but not limited to, platinum, rhodium, ruthenium, and the like.
A second gate insulating layer 120 is formed over the noble metal nano-crystals 115. The nano-crystals 115 are formed to be separate and isolated crystals. The second gate insulating layer 120 is formed over and between the nano-crystals 115. The second gate insulating layer 120 can be any suitable insulating material including, but not limited to, Al2O3, or HfO2.
A barrier layer or silicon dioxide layer (not shown) can be formed over second gate insulating layer 120 when the second gate insulating layer is a high constant dielectric layer.
A polysilicon gate layer 125 is formed on the second gate insulating layer 120. The polysilicon gate layer 125 can be made of materials including, but not limited to, polysilicon, tungsten, tungsten-nitride, polysilicon/tungsten-silicide, polysilicon/tungsten-silicide/tungsten, and polysilicon/tungsten-nitride/tungsten.
An insulating layer 130 is formed on the polysilicon gate layer 125. The insulating layer 130 can be made of suitable insulating materials including, but not limited to, silicon oxide, or silicon nitride.
During manufacture of the device, removing of various layers is required. When the nano-crystals are made of platinum, removing the platinum nano-crystals is difficult. Platinum etch processes are predominantly physical, as opposed to chemical, etches. One typical platinum etch process involves biasing the chuck on which the device is placed and sputtering the platinum to remove it. However, the sputtering process has very low etch selectivity for the underlying tunnel oxide layer. The tunnel oxide is attacked during the sputtering process and damaged.
Therefore, there is a need for an improved removal process for nano-crystals.